VLSI Implementation of a Soft-Output Signal Detector for Multi-Mode Adaptive MIMO Systems

This paper presents a multi-mode soft-output multiple-input multiple-output (MIMO) signal detector that is efficient in hardware cost and energy consumption. The detector is capable of dealing with spatial-multiplexing (SM), space-divisionmultiple-access (SDMA), and spatial-diversity (SD) signals of 4×4 antenna and 64-QAM modulation. Implementation-friendly algorithms, which reuse most of the mathematical operations in these three MIMO modes, are proposed to provide accurate soft detection information, i.e., log-likelihood ratio (LLR), with much reduced complexity. A unified reconfigurable VLSI architecture has been developed to eliminate the implementation of multiple detector modules. In addition, several block level technologies, such as parallel metric update and fast bit-flipping, are adopted to enable a more efficient design. To evaluate the proposed techniques, we implemented the triple-mode MIMO detector in a 65-nm CMOS technology. The core area is 0.25 mm with 83.7 K gates. The maximum detecting throughput is 1 Gb/s at 167-MHz clock frequency and 1.2-V supply, which archives the data rate envisioned by the emerging long-term evolution advanced (LTEA) standard. Under frequency-selective channels, the detector consumes 59.3 pJ, 10.5 pJ, and 169.6 pJ energy per bit detection in SM, SD, and SDMA modes, respectively.